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tsc8051c1 rev. d (14 jan. 97) 1 matra mhs 1. introduction the tsc8051c1 is a standalone high performance cmos 8bit embedded microcontroller and is designed for use in crt monitors. it is also suitable for automotive and industrial applications. the tsc8051c1 includes the fully static 8bit a80c51o cpu core with 256 bytes of ram; 8 kbytes of rom; two 16bit timers; 12 pwm channels; a 6 sources and 2level interrupt controller; a full duplex serial port; a full i 2 c ? * interface; a watchdog timer and onchip oscillator. in addition, the tsc8051c1 has 2 software selectable modes of reduced activity for further reduction in power consumption. in the idle mode the cpu is frozen while the ram, the timers, the serial ports, and the interrupt system continue to function. in the power down mode the ram is saved and all other functions are inoperative. the tsc8051c1 enables the users reducing a lot of external discrete components while bringing the maximum of flexibility. 2. features boolean processor fully static design 8k bytes of rom 256 bytes of ram 2 x 16bit timer/counter programmable serial port programmable multimaster i 2 c controller 6 interrupt sources: external interrupts (2) timers interrupt (2) serial port interrupt i 2 c interrupt watchdog reset on chip oscillator for crystal or ceramic resonator 2 power saving control modes: idle mode powerdown mode controlled hsync & vsync outputs up to 12 programmable pwm channels with 8bit resolution up to 32 programmable i/o lines depending on the package 40 pins dip, 44 pins pqfp, 44 and 52 pins plcc packages commercial and industrial temperature ranges operating frequency: 12 mhz to 16 mhz 8-bit microcontroller for digital computer monitors * i2c is a trademark of philips corporation
tsc8051c1 rev. d (14 jan. 97) 2 matra mhs 3. block diagram xtal2 alternate function of port0 alternate function of port2 alternate function of port1 alternate function of port3 1 80c51 core excluding rom/ram program memory 8k x 8 rom data memory 256 x 8 ram serial i 2 c port two 16bit timer/event counter cpu serial uart port parallel i/o ports and external bus ad07 rst a815 3 3 0 2 3 3 3 3 3 3 3 3 3 2 1 0 pwm8 pwm11 pwm0 pwm7 vcc vss int0 t0 t1 int1 t0 int0 sda scl p0 p1 p2 p3 txd rxd 12 x 8bit pwm channels watchdog timer controlled hsync & vsync outputs xtal1 ea ale psen wr rd special external inputs 3 3 3 3 vsync hsync vout hout 8bit internal bus figure 1. tsc8051c1 block diagram.
tsc8051c1 rev. d (14 jan. 97) 3 matra mhs 4. pin configurations p3.1/txd 11 psen 12 ea 10 p3.2/int0 /vsync p3.0/rxd dil 40 vcc p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ale pwm7 * pwm6 * pwm5 * pwm4 * pwm3 * pwm2 * pwm1 * pwm0 * p1.0/pwm8 p1.1/pwm9 p1.2/pwm10 p1.3/pwm11 p1.4 p1.5 p1.6 p1.7 rst p3.3/int1 /vout p3.4/to/hsync p3.5/t1/hout p3.6/wr /scl p3.7/rd /sda xtal2 xtal1 vss 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 23 22 21 29 31 32 28 27 26 25 24 30 *pwmx or p2.x depending on option (see ordering information) 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 47 48 49 50 51 52 1 2 3 4 5 6 7 34 35 36 37 38 39 40 41 42 43 44 45 46 plcc 52 index corner p0.5 p0.6 p0.7 ea ale psen p2.7 pwm7 p2.6 pwm6 p2.5 pwm5 pwm4 nc p1.5 p1.6 p1.7 rst p3.0/rxd p3.1/txd p3.2/int0 /vsync p3.3/int1 /vout p3.4/t0/hsync p3.5/t1/hout nc p3.6/wr /scl p1.4 p1.3/pwm11 p1.2/pwm10 p1.1/pwm9 p1.0/pwm8 nc vcc p0.0 p0.1 p0.2 p0.3 nc p0.4 p3.7/rd/sda xtal2 xtal1 vss pwm0 pwm1 pwm2 pwm3 p2.0 p2.1 p2.2 p2.3 p2.4 figure 2. tsc8051c1 pin configurations. 2 3 4 5 12 6 7 39 8 9 10 11 35 36 37 38 plcc 44 p1.5 p1.6 p1.7 rst p3.0/rxd nc p3.1/txd p3.2/int0 /vsync pwm7* pwm6* pwm5* 28 26 26 24 23 22 21 20 19 18 17 16 15 14 13 40 41 42 43 44 1 29 30 31 32 33 34 index corner p0.4 p0.5 p0.6 p0.7 ea nc ale psen pwm7* pwm6* pwm5* 27 p1.4 p1.3/pwm11 p1.2/pwm10 p1.1/pwm9 p1.0/pwm8 nc vcc p0.0 p0.1 p0.2 p0.3 p3.6/wr/scl p3.7/rd/sda xtal2 xtal1 vss nc pwm0* pwm1* pwm2* pwm3* pwm4*
tsc8051c1 rev. d (14 jan. 97) 4 matra mhs 5. pin description vss circuit ground. vcc power supply voltage. rst a high level on this pin for two machine cycles while the oscillator is running resets the device. an internal pulldown resistor permits poweron reset using only a capacitor connected to vcc. port 0 (p0.0p0.7) port 0 is an 8bit opendrain bidirectional i/o port. port 0 pins that have 1's written to them float, and in that state can be used as highimpedance inputs. port 0 is also the multiplexed loworder address and data bus during access to external program and data memory. in this application it uses strong internal pullup when emitting 1's. port 0 can sink and source 8 ls ttl loads. port 1 (p1.0p1.7) port 1 is an 8bit bidirectional i/o port with internal pullups. port 1 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current (iil on the datasheet) because of the internal pullups. port 1 also serves 4 programmable pwm open drain outputs, as listed below: port pin alternate function p1.0 pwm8: pulse width modulation output 8. p1.1 pwm9: pulse width modulation output 9. p1.2 pwm10: pulse width modulation output 10. p1.3 pwm11: pulse width modulation output 11. port 1 can sink and source 3 ls ttl loads. port 2 (p2.0p2.7) port 2 is an 8bit bidirectional i/o port with internal pullups. port 2 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current (iil on the datasheet) because of the internal pullups. port 2 emits the highorder 8bit address during fetches from external program memory and during accesses to external data memory that use 16bit addresses. in this application it uses strong internal pullup when emitting 1's. port 2 can sink and source 3 ls ttl loads. port 3 (p3.0p3.7) port 3 is an 8bit bidirectional i/o port with internal pullups. port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (iil on the datasheet) because of the internal pullups. each line on this port has 2 or 3 functions either a general i/o or special control signal, as listed below: port pin alternate function p3.0 rxd: serial input port. p3.1 txd: serial output port. p3.2 int0 : external interrupt 0. vsync: vertical synchro input. p3.3 int1 : external interrupt 1. vout: buffered v-sync output. p3.4 t0: timer 0 external input. hsync: horizontal synchro input. p3.5 t1: timer 1 external input. hout: buffered hsync output. p3.6 wr : external data memory write strobe. scl: serial port clock line i 2 c bus. p3.7 rd : external data memory read strobe. sda: serial port data line i 2 c bus. port 3 can sink and source 3 ls ttl loads. pwm07 these eight pulse width modulation outputs are true open drain outputs and are floating after reset. ale the address latch enable output signal occurs twice each machine cycle except during external data memory access. the negative edge of ale strobes the address into external data memory or program memory. ale can sink and source 8 ls ttl loads. if desired, ale operation can be disabled by setting bit 0 of sfr location afh (mscon). with the bit set, ale is active only during movx instruction and external fetches. otherwise the pin is pulled low.
tsc8051c1 rev. d (14 jan. 97) 5 matra mhs ea when the external access input is held high, the cpu executes out of internal program memory (unless the program counter exceeds 1fffh). when ea is held low the cpu executes only out of external program memory. must not be left floating. psen the program store enable output signal remains high during internal program memory. an active low output occurs during an external program memory fetch. psen can sink and source 8 ls ttl loads. xtal1 input to the inverting oscillator amplifier and input to the external clock generator circuits. xtal2 output from the inverting oscillator amplifier. this pin should be nonconnected when external clock is used.
tsc8051c1 rev. d (14 jan. 97) 6 matra mhs 6. basic functional description 6.1. idle and power down operation figure 3 shows the internal idle and power down clock configuration. as illustrated, power down operation stops the oscillator. idle mode operation allows the interrupt, serial port, and timer blocks to continue to operate while the clock to the cpu is gated off. these special modes are activated by software via the special function register, its hardware address is 87h. pcon is not bit addressable. osc clock gen. interrupt serial port timer blocks cpu idl xtal2 xtal1 pd figure 3. idle and power down hardware. pcon: power control register msb sfr 87h lsb smod gf1 gf0 pd idl symbol position name and function idl pcon.0 idle mode bit. setting this bit activates idle mode operation. pd pcon.1 power down bit. setting this bit activates power down operation. gf0 pcon.2 generalpurpose flag bit. gf1 pcon.3 generalpurpose flag bit. pcon.4 (reserved). pcon.5 (reserved). pcon.6 (reserved). smod pcon.7 double baud rate bit. setting this bit causes the baud rate to double when the serial port is being used in either modes 1, 2 or 3. if 1's are written to pd and idl at the same time, pd takes precedence. the reset value of pcon is 0xxx0000b. 6.1.1. idle mode the instruction that sets pcon.0 is the last instruction executed before the idle mode is activated. once in the idle mode the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, ram, and all other register maintain their data during idle table 1 describes the status of the external pins during idle mode. there are two ways to terminate the idle mode. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware terminating idle mode. the interrupt is serviced, and following reti, the next instruction to be executed will be the one following the instruction that wrote 1 to pcon.0. the flag bits gf0 and gf1 may be used to determine whether the interrupt was received during normal execution or during the idle mode. for example, the instruction that writes to pcon.0 can also set or clear one or both flag bits. when idle mode is terminated by an enabled interrupt, the service routine can examine the status of the flag bits. the second way of terminating the idle is with a hardware reset. since the oscillator is still running, the hardware reset needs to be active for only 2 machine cycles (24 oscillator periods) to complete the reset operation.
tsc8051c1 rev. d (14 jan. 97) 7 matra mhs 6.1.2. power down mode the instruction that sets pcon.1 is the last executed prior to entering power down. once in power down, the oscillator is stopped. the contents of the onchip ram and the special function register are saved during power down mode. a hardware reset is the only way of exiting the power down mode. the hardware reset initiates the special function register. in the power down mode, vcc may be lowered to minimize circuit power consumption. care must be taken to ensure the voltage is not reduced until the power down mode is entered, and that the voltage is restored before the hardware reset is applied which frees the oscillator. reset should not be released until the oscillator has restarted and stabilized. table 1 describes the status of the external pins while in the power down mode. it should be noted that if the power down mode is activated while in external program memory, the port data that is held in the special function register p2 is restored to port 2. if the data is a 1, the port pin is held high during the power down mode by the strong pullup transistor. table 1. status of the external pins during idle and power down modes. mode program memory ale psen port 0 port 1 port 2 port 3 pwmx idle internal 1 1 port data port data port data port data floating idle external 1 1 floating port data address port data floating power down internal 0 0 port data port data port data port data floating power down external 0 0 floating port data port data port data floating 6.2. stop clock mode due to static design, the tsc8051c1 clock speed can be reduced down to 0 mhz without any data loss in memory or register. this mode allows step by step code execution, and permits to reduce system power consumption by bringing the clock frequency down to any value. when the clock is stopped, the power consumption is the same as in the power down mode. 6.3. i/o ports structure the tsc8051c1 has four 8bit ports. each port consist of a latch (special function register p0 to p3), an input buffer and an output driver. these ports are the same as in 80c51, with the exception of the additional functions of port 1 and port 3 (see pin description section). 6.4. i/o configurations figure 4. shows a functional diagram of the generic bit latch and i/o buffer in each of the four ports. the bit latch, (one bit in the port sfr) is represented as a d type flipflop. a `write to latch' signal from the cpu latches a bit from the internal bus and a `read latch' signal from the cpu places the q output of the flipflop on the internal bus. a `read pin' signal from the cpu places the actual pin logical level on the internal bus. some instructions that read a port read the actual pin, and other instructions read the latch (sfr).
tsc8051c1 rev. d (14 jan. 97) 8 matra mhs port 0 bit to le q write latch mux latch write latch write to write to latch to latch read latch mux port 1 bit dq p0.x p0.x pin vcc control addr/data int. bus pin read latch dq p1.x latch le q p1.x pin vcc control pwmx int. bus read pin internal pullup* read latch dq p2.x le q p2.x pin vcc control addr int. bus read pin internal pullup read latch dq p3.x latch le q p3.x pin vcc sio1 control* int. bus alternate output function * internal pullup not present on p3.6 and p3.7 when sio1 is enabled. alternate input function read pin internal pullup* read latch port 2 bit port 3 bit mux * internal pullup not present on p1.0 to p1.3 when pwm8 to pwm11 are enabled figure 4. port bit latches and i/o buffers 6.5. reset circuitry the reset circuitry for the tsc8051c1 is connected to the reset pin rst. a schmitt trigger is used at the input for noise rejection (see figure 5. ). a reset is accomplished by holding the rst pin high for at least two machine cycles (24 oscillator periods) while the oscillator is running. the cpu responds by executing an internal reset. it also configures the ale and psen pins as inputs (they are quasibidirectional). a watchdog timer underflow if enabled, will force a reset condition to the tsc8051c1 by an internal connection. the internal reset is executed during the second cycle in which reset is high and is repeated every cycle until rst goes low. it leaves the internal registers as follows: register content acc 00h b 00h dptr 0000h eicon 00h hwdr 00h ie 0x000000b ip xx000000b mscon xxxxxxx0b mxcr01 00h p0p3 ffh
tsc8051c1 rev. d (14 jan. 97) 9 matra mhs register content pc 0000h pcon 0xxx0000b psw 00h pwm011 00h pwmcon xxxxxxx0b s1con 00h s1dat 00h s1sta f8h sbuf 00h scon 00h socr 00h sp 07h tcon 00h th0, th1 00h tl0, tl1 00h tmod 00h the internal ram is not affected by reset. at poweron reset, the ram content is indeterminate. watchdog reset rst reset circuitry schmitt trigger onchip resistor r rst figure 5. onchip reset configuration. an automatic reset can be obtained when vcc is turned on by connecting the rst pin to vcc through a 1 m f capacitor providing the vcc setting time does not exceed 1ms and the oscillator startup time does not exceed 10ms. this poweron reset circuit is shown in figure 6. when power comes on, the current drawn by rst starts to charge the capacitor. the voltage at rst is the difference between vcc and the capacitor voltage, and decreases from vcc as the capacitor charges. v rst must remain above the lower threshold of the schmitt trigger long enough to effect a complete reset. the time required is the oscillator startup time, plus 2 machine cycles. + vss rst v rst r rst vcc tsc8051c1 vcc 1 f figure 6. poweron reset circuit 6.6. oscillator characteristics xtal1 and xtal2 are respectively the input and output of an inverting amplifier which is configured for use as an onchip oscillator. as shown in figure 7. , either a quartz crystal or ceramic resonator may be used. to drive the device from an external clock source, xtal1 should be driven while xtal2 is left unconnected as shown in figure 8. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a dividebytwo flipflop. the minimum high and low times specified on the data sheet must be observed however. xtal2 xtal1 vss figure 7. crystal oscillator xtal2 xtal1 vss nc external oscillator signal figure 8. external drive configuration
tsc8051c1 rev. d (14 jan. 97) 10 matra mhs 6.7. memory organization the memory organisation of the tsc8051c1 is the same as in the 80c51, with the exception that the tsc8051c1 has 8k bytes rom, 256 bytes ram, and additional sfrs. details of the differences are given in the following paragraphs. in the tsc8051c1, the lowest 8k of the 64k program memory address space is filled by internal rom. depending on the package used, external access is available or not. by tying the ea pin high, the processor fetches instructions from internal program rom. bus expansion for accessing program memory from 8k upward is automatic since external instruction fetches occur automatically when the program counter exceeds 1fffh. if the ea pin is tied low, all program memory fetches are from external memory. the execution speed is the same regardless of whether fetches are from external or internal program memory. if all storage is onchip, then byte location 1fffh should be left vacant to prevent an undesired prefetch from external program memory address 2000h. certain locations in program memory are reserved for specific purposes. locations 0000h to 0002h are reserved for the initialisation program. following reset, the cpu always begins execution at location 0000h. locations 0003h to 0032h are reserved for the six interrupt request service routines. the internal data memory space is divided into a 256bytes internal ram address space and a 128 bytes special function register address space. the internal data ram address space is 0 to ffh. four 8bit register banks occupy locations 0 to 1fh. 128 bit locations of the internal data ram are accessible through direct addressing. these bits reside in 16 bytes of internal ram at location 20h to 2fh. the stack can be located anywhere in the internal data ram address space by loading the 8bit stack pointer (sp sfr). the sfr address space is 100h to 1ffh. all registers except the program counter and the four 8bit register banks reside in this address space. memory mapping of the sfrs allows them to be accessed as easily as internal ram, and as such, they can be operated on by most instructions.the mapping in the sfr address space of the 43 sfrs is shown in table 2. the sfr names in italic are tsc8051c1 new sfrs and are described in peripherals functional description section. the sfr names in bold are bit addressable.
tsc8051c1 rev. d (14 jan. 97) 11 matra mhs table 2. mapping of special function register 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8 pwm8 pwm9 pwm10 pwm11 f0 b pwm4 pwm5 pwm6 pwm7 e8 pwm0 pwm1 pwm2 pwm3 e0 acc eicon socr hwdr mxcr0 d8 s1con s1sta s1dat pwmcon d0 psw mxcr1 c8 c0 b8 ip b0 p3 a8 ie mscon a0 p2 98 scon sbuf 90 p1 88 tcon tmod tl0 tl1 th0 th1 80 p0 sp dpl dph pcon 6.8. interrupts the tsc8051c1 has six interrupt sources, each of which can be assigned one of two priority levels. the five interrupt sources common to the 80c51 are the external interrupts (int0 and int1), the timer 0 and timer 1 interrupts (it0 and it1), and the serial i/o interrupt (ri or ti). in the tsc8051c1, the standard serial i/o is called sio0. the sio1 (i 2 c) interrupt is generated by the si flag in the control register (s1con sfr). this flag is set when the status register (s1sta sfr) is loaded with a valid status code. 6.8.1. interrupt enable register: each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable register (ie sfr). all interrupts sources can also be globally enabled or disabled by setting or clearing the ea bit in ie register.
tsc8051c1 rev. d (14 jan. 97) 12 matra mhs ie: interrupt enable register msb sfr a8h lsb ea es1 es0 et1 ex1 et0 ex0 symbol position name and function ex0 ie.0 enable external interrupt 0. et0 ie.1 enable timer 0 interrupt. ex1 ie.2 enable external interrupt 1. et1 ie.3 enable timer 1 interrupt. es0 ie.4 enable sio0 (uart) interrupt. es1 ie.5 enable sio1 (i 2 c) interrupt. ie.6 (reserved). ea ie.7 enable all interrupts. 6.8.2. interrupt priority structure: each interrupt source can be assigned one of two priority levels. interrupt priority levels are defined by the interrupt priority register (ip sfr). setting a bit in the interrupt priority register selects a high priority interrupt, clearing it selects a low priority interrupt. ip: interrupt priority register msb sfr b8h lsb ps1 ps0 pt1 px1 pt0 px0 symbol position name and function px0 ip.0 external interrupt 0 priority level. pt0 ip.1 timer 0 interrupt priority level. px1 ip.2 external interrupt 1 priority level. pt1 ip.3 timer 1 interrupt priority level. ps0 ip.4 sio0 (uart) interrupt priority level. ps1 ip.5 sio1 (i 2 c) interrupt priority level. ip.6 (reserved). ip.7 (unused). a low priority interrupt service routine may be interrupted by a high priority interrupt. a high priority interrupt service routine cannot be interrupted by any other interrupt source. if two requests of different priority levels occur simultaneously, the high priority level request is serviced. if requests of same priority are received simultaneously, an internal polling sequence determines which request is serviced. thus, within each priority level, there is a second priority structure determined by the polling sequence, as follows:
tsc8051c1 rev. d (14 jan. 97) 13 matra mhs order source priority within level 1 int0 (highest) 2 timer 0 3 int1 4 timer 1 5 sio0 6 sio1 (lowest) 6.8.3. interrupt handling: the interrupt flags are sampled at s5p2 of every machine cycle. the samples are polled during the following machine cycle. if one of the flags was in a set condition at s5p2 of the previous machine cycle, the polling cycle will find it and the interrupt system will generate a lcall to the appropriate service routine, provided this hardwaregenerated lcall is not blocked by any of the following conditions: 1. an interrupt of higher or equal priority is already in progress. 2. the current (polling) cycle is not the final cycle in the execution of the instruction in progress. 3. the instruction in progress is reti or any access to the ie or ip sfr. any of these three conditions will block the generation of the lcall to the interrupt service routine. note that if an interrupt is active but not being responded to for one of the above conditions, if the flag is not still active when the blocking condition is removed, the denied interrupt will not be serviced. in other words, the facts that the interrupt flag was once active but not serviced is not memorized. every polling cycle is new. the processor acknowledges an interrupt request by executing a hardwaregenerated lcall to the appropriate service routine. in some cases it also clears the flag that generated the interrupt, and in other case it does not. it clears the timer 0, timer 1, and external interrupt flags. an external interrupt flag (ie0 or ie1) is cleared only if it was transitionactivated. all other interrupt flags are not cleared by hardware and must be cleared by the software. the lcall pushes the contents of the program counter onto the stack (but it does not save the psw) and reloads the pc with an address that depends on the source of the interrupt being vectored to, as listed below: source vector address ie0 0003h tf0 000bh ie1 0013h tf1 001bh ri + ti 0023h si 002bh execution proceeds from the vector address until the reti instruction is encountered. the reti instruction clears the `priority level active' flipflop that was set when this interrupt was acknowledged. it then pops two bytes from the the top of the stack and reloads the program counter with them. execution of the interrupted program continues from where it was interrupted.
tsc8051c1 rev. d (14 jan. 97) 14 matra mhs 7. peripherals functional description for detailed functionnal description of standard 80c51 peripherals, please refer to c51 family, hardware description and programmer's guides. 7.1. watchdog timer the watchdog timer consists of a 4bit timer with a 17bit prescaler as shown in figure 9. the prescaler is fed with a signal whose frequency is 1/12 the oscillator frequency (1mhz with a 12mhz oscillator). the 4bit timer is decremented every `t' seconds, where: t = 12 x 131072 x 1/fosc. (131.072ms at fosc = 12mhz). thus, the interval may vary from 131.072ms to 2097.152ms in 16 possible steps (see table 3. ). the watchdog timer has to be reloaded (write to hwdr sfr) within periods that are shorter than the programmed watchdog interval, otherwise the watchdog timer will underflow and a system reset will be generated which will reset the tsc8051c1. hwdr: hardware watchdog register msb sfr e6h lsb wte wt3 wt2 wt1 wt0 symbol position name and function wt0 hwdr.0 watchdog timer interval bit 0. wt1 hwdr.1 watchdog timer interval bit 1. wt2 hwdr.2 watchdog timer interval bit 2. wt3 hwdr.3 watchdog timer interval bit 3. hwdr.4 reserved for test purpose, must remain to 0 for normal operation. hwdr.5 (reserved). hwdr.6 (reserved). wte hwdr.7 watchdog timer enable bit. setting this bit activates watchdog operation. table 3. watchdog timer interval value format. wt3 wt2 wt1 wt0 interval 0 0 0 0 t x 16 0 0 0 1 t x 1 0 0 1 0 t x 2 : : : : : : : : : : 1 1 1 1 t x 15 once the watchdog timer enabled setting wte bit, it cannot be disabled anymore, except by a system reset. the watchdog timer is frozen during idle or power down mode. hwdr is a write only register. its value after reset is 00h which disables the watchdog operation. hwdr is using tsc8051c1 special function register address, e6h. timer (4bit) prescaler (17bit) load clear underflow wte internal reset set internal bus write hwdr fosc/12 q figure 9. watchdog timer block diagram
tsc8051c1 rev. d (14 jan. 97) 15 matra mhs 7.2. pulse width modulated outputs the tsc8051c1 contains twelve pulse width modulated output channels (see figure 10. ). these channels generate pulses of programmable duty cycle with an 8bit resolution. the 8bit counter counts modulo 256 by default i.e., from 0 to 255 inclusive but can count modulo 254 i.e., from 0 to 253 inclusive by programming the bit 0 of the pwmcon register. the counter clock is supplied by the oscillator frequency. thus, the repetition frequency fpwm is constant and equals to the oscillator frequency divided by 256 or 254 (fpwm=46.875khz or 47.244khz with a 12mhz oscillator). the 8bit counter is common to all pwm channels, its value is compared to the contents of the twelve registers: pwm0 to pwm11. provided the content of each of these registers is greater than the counter value, the corresponding output is set low. if the contents of these registers are equal to, or less than the counter value the output will be high. the pulsewidth ratio is therefore defined by the contents of these registers, and is in the range of 0 (all `0' written to pwm register) to 255/256 or 1 (all `1' written to pwm register) and may be programmed in increments of 1/256 or 1/254. when the 8bit counter counts modulo 254, it can never reach the value of the pwm registers when they are loaded with feh or ffh. pwmx: pulse width modulator x register msb lsb d7 d6 d5 d4 d3 d2 d1 d0 when a compare register (pwm0 to pwm11) is loaded with a new value, the associated output is updated immediately. it does not have to wait until the end of the current counter period. all the pwm outputs are opendrain outputs with standard current drive and standard maximum voltage capability. when they are disabled, eight of them (pwm0 to pwm7) are in high impedance while the other four (pwm8 to pwm11) are standard port outputs with internal pullups. pwm0 to pwm11 are write only registers. their value after reset is 00h. pwm0 to pwm11 are using tsc8051c1 special function registers addresses as detailed in table 4. table 4. pwm sfr register addresses channel sfr address pwm0 ech pwm1 edh pwm2 eeh pwm3 efh pwm4 f4h pwm5 f5h pwm6 f6h pwm7 f7h pwm8 fch pwm9 fdh pwm10 feh pwm11 ffh two 8bit control registers: mxcr0 and mxcr1 are used to enable or disable pwm outputs. mxcr0 is used for pwm0 to pwm7. mxcr1 is used for pwm8 to pwm11, these pwms are multiplexed with port 1 (see table 5. )
tsc8051c1 rev. d (14 jan. 97) 16 matra mhs mxcr0: pwm multiplexed control register 0 msb sfr e7h lsb pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 symbol position name and function pex mxcr0.x pwm x enable bit. setting this bit enables pwmx output. clearing this bit disables pwmx output. mxcr1: pwm multiplexed control register 1 msb sfr d7h lsb pe11 pe10 pe9 pe8 symbol position name and function pex mxcr1.x pwm x+8 enable bit. setting this bit enables pwmx output. clearing this bit disables pwmx output and activates the i/o pin (see table 5). mxcr0 and mxcr1 are read/write registers. their value after reset is 00h which corresponds to all pwm disabled. pwm will not operate in idle and power down modes (frozen counter). when idle or power down mode is entered, the pwm0 to pwm7 output pins are floating and pwm8 to pwm11 pins are set to general purpose p1 port with the value of p1 sfr. mxcr0 and mxcr1 are using tsc8051c1 special function register addresses, e7h and d7h respectively. table 5. pwm alternate pin. channel pin assignment pwm8 p1.0 pwm9 p1.1 pwm10 p1.2 pwm11 p1.3 pwmcon is used to control the pwm counter. pwmcon: pwm control register msb sfr dfh lsb cmod symbol position name and function cmod pwmcon.0 counter modulo. setting this bit sets the modulo to 254. clearing this bit sets the modulo to 256. pwmcon is a write only register. its value after reset is 00h which sets the pwm counter modulo to 256. pwmcon is using tsc8051c1 special function register address, dfh.
tsc8051c1 rev. d (14 jan. 97) 17 matra mhs 8bit counter internal bus pwmx register output buffer x 8bit comparator x pwmx fosc cmod bit pex bit figure 10. pulse width modulated outputs block diagram figure 11. shows a pwm programming example with pwm register content 55h and counter modulo 256. 55h abh 100h figure 11. pwm programming example. note: when packaging p2.x is selected, pwm0 to pwm7 are not available. please refer to ordering information. 7.3. controlled hsync and vsync outputs socr is used to configure p3.3 and p3.5 pins as buffered hsync and vsync outputs or as general purpose i/os. when either hsync or vsync is selected, the output level can be respectively programmed as p3.4 or p3.2 input level (inverted or not), or as a low level if not enabled. figure 12. shows the programmable hsync and vsync output block diagram. socr: synchronisation output control register. msb sfr e5h lsb vos hos vop voe hop hoe symbol position name and function hoe socr.0 hsync output enable bit. setting this bit enables the hsync signal. hop socr.1 hsync output polarity bit. setting this bit inverts the hsync output. voe socr.2 vsync output enable bit. setting this bit enables the vsync signal. vop socr.3 vsync output polarity bit. setting this bit inverts the vsync output. hos socr.4 hsync output selection bit. setting this bit selects the vsync output, clearing it selects p3.5 sfr bit. vos socr.5 vsync output selection bit. setting this bit selects the vsync output, clearing it selects p3.3 sfr bit. socr is a write only register. its value after reset is 00h which enables p3.3 and p3.5 general purpose i/o pins. socr is using tsc8051c1 special function register address, e5h.
tsc8051c1 rev. d (14 jan. 97) 18 matra mhs hop pin p3.4/t0/hsync p3.5/hout pin 8051 core p3.5 hoe hos mux vop pin p3.2/int0 /hsync p3.3/vout pin 8051 core p3.3 voe vos mux figure 12. buffered hsync and vsync block diagram 7.4. hsync and vsync inputs eicon is used to control int0 vsync input. thus, an interrupt on either falling or rising edge and on either high or low level can be requested. figure 13. shows the programmable int0 /vsync input block diagram. eicon is also used to control t0/hsync input as short pulses input capture to be able to count them with timer 0. pulse duration shorter than 1 clock period is rejected; depending on the position of the sampling point in the pulse, pulse duration longer than 1 clock period and shorter than 1.5 clock period may be rejected or accepted; and pulse duration longer than 1.5 clock period is accepted. moreover selection of negative or positive pulses can be programmed. accepted pulse is lengthened up to 1 cycle period to be sampled by the 8051 core (one time per machine cycle: 12 clock periods), this implies that the maximum pulse frequency is unchanged and equal to f osc /24. figure 14. shows the programmable t0/hsync input block diagram. the digital timer delay samples t0/hsync pulses and rejects or lengthens them. eicon: external input control register msb sfr e4h lsb t0l t0s i0l symbol position name and function i0l eicon.0 int0 /vsync input level bit. setting this bit inverts int0 /vsync input signal. clearing it allows standard use of int0 /vsync input. t0s eicon.1 t0/hsync input selection bit. setting this bit allows short pulse capture. clearing it allows standard use of t0/hsync input. t0l eicon.2 t0/hsync input level bit. setting this bit allows positive pulse capture. clearing it allows negative pulse capture. eicon is a write only register. its value after reset is 00h which allows standard int0 and t0 inputs feature. eicon is using tsc8051c1 special function register address, e4h. int0 p3.2/int0 /vsync pin mux i0l figure 13. int0 /vsync input block diagram p3.4/t0/hsync digital time delay pin t0 mux t0s t0l f osc figure 14. t0/hsync input block diagram 7.5. sio1, i 2 c serial i/o sio1 provides a serial interface that meets the i 2 c bus specification and supports the master transfer modes with multimaster capability from and to the i 2 c bus. the sio1 logic handles bytes transfer autonomously. it also keeps track of serial transfers and a status register reflects the status of sio1 and the i 2 c bus.
tsc8051c1 rev. d (14 jan. 97) 19 matra mhs figure 15. shows a typical use of i 2 c bus with sio1, and figure 16. shows a complete data transfer with sio1. rp scl/p3.6 sda/p3.7 tsc8051c1 device 2 device n device 1 rp figure 15. typical i 2 c bus configuration r/w direction acknowledgment signal from receiver msb scl sda s p/s acknowledgment signal from receiver slave address nth data byte clock line held low while interrupts are serviced 12 89 bit 12 89 figure 16. complete data transfer on i 2 c bus three 8bit special function registers are used to control sio1: the control register (s1con sfr), the status register (s1sta sfr) and the data register (s1dat sfr). s1con is used to enable sio1, to program the bit rate (see table 6. ), to acknowledge or not a received data, to send a start or a stop condition on the i 2 c bus, and to acknowledge a serial interrupt. s1con: synchronous serial control register msb sfr d8h lsb cr2 ens1 sta sto si aa cr1 cr0 symbol position name and function cr0 s1con.0 control rate bit 0. see table 6. cr1 s1con.1 control rate bit 1. see table 6. aa s1con.2 assert acknowledge flag. in receiver mode, setting this bit forces an acknowledge (low level on sda). in receiver mode, clearing this bit forces a not acknowledge (high level on sda). when in transmitter mode, this bit has no effect. si s1con.3 synchronous serial interrupt flag. this bit is set by hardware when a serial interrupt is requested. this bit must be reset by software to acknowledge interrupt. st0 s1con.4 stop flag. setting this bit causes a stop condition to be sent on bus. sta s1con.5 start flag. setting this bit causes a start condition to be sent on bus. ens1 s1con.6 synchronous serial enable bit. setting this bit enables the sio1 controller. cr2 s1con.7 control rate bit 2. see table 6. s1con is a read/write. its value after reset is 00h which disables the i 2 c controller. s1con is using tsc8051c1 special function register address, d8h.
tsc8051c1 rev. d (14 jan. 97) 20 matra mhs table 6. serial clock rates bit frequency (khz) cr2 cr1 cr0 6mhz 12mhz fosc divided by 0 0 0 23.5 47 256 0 0 1 27 53.5 224 0 1 0 31.25 62.5 192 0 1 1 37.5 75 160 1 0 0 6.25 12.5 960 1 0 1 50 100 120 1 1 0 100 60 1 1 1 0.25<62.5 0.5<62.5 timer 1 overflow 96 x (256 reload value) value: 0254 in mode 2 s1sta contains a status code which reflects the status of sio1 and the i 2 c bus. the three least significant bits are always zero. the five most significant bits contains the status code. there are 12 possible status code. when s1sta contains f8h, no relevant state information is available and no serial interrupt is requested. a valid status code is available in s1sta one machine cycle after si is set by hardware and is still present one machine cycle after si has been reset by software. table 7. to table 9. give the status for the operating modes and miscellaneous states. s1sta: synchronous serial status register msb sfr d9h lsb sc4 sc3 sc2 sc1 sc0 0 0 0 symbol position name and function sc0 s1sta.3 status code bit 0. sc1 s1sta.4 status code bit 1. sc2 s1sta.5 status code bit 2. sc3 s1sta.6 status code bit 3. sc4 s1sta.7 status code bit 4. s1sta is a read only register. its value after reset is f8h. s1sta is using tsc8051c1 special function register address, d9h.
tsc8051c1 rev. d (14 jan. 97) 21 matra mhs table 7. status for master transmitter mode. status code status of i 2 c bus and sio1 hardware 08h a start condition has been transmitted. 10h a repeated start condition has been transmitted 18h sla+w has been transmitted; ack has been received. 20h sla+w has been transmitted; not ack has been received. 28h data byte has been transmitted; ack has been received. 30h data byte has been transmitted; not ack has been received. 38h arbitration lost in sla+r/w or data bytes. table 8. status for master receiver mode status code status of i 2 c bus and sio1 hardware 08h a start condition has been transmitted. 10h a repeated start condition has been transmitted. 38h arbitration lost in not ack bit 40h sla+r has been transmitted; ack has been received. 48h sla+r has been transmitted; not ack has been received. 50h data byte has been received; ack has been received. 58h data byte has been received; not ack has been received. table 9. status for miscellaneous states status code status of i 2 c bus and sio1 hardware 00h bus error. f8h no relevant state information available. s1dat contains a byte of serial data to be transmitted or a byte which has just been received. it is addressable while it is not in process of shifting a byte. this occurs when sio1 is in a defined state and the serial interrupt flag is set. data in s1dat remains stable as long as si is set. while data is being shifted out, data on the bus is simultaneously shifted in; s1dat always contains the last byte present on the bus. s1dat: synchronous serial data register msb sfr dah lsb sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 symbol position name and function sd0 s1dat.0 address bit 0 (r/w ) or data bit 0. sdx s1dat.x address bit x or data bit x. s1dat is a read/write register. its value after reset is 00h. s1dat is using tsc8051c1 special function register address, dah. when sio1 is enabled, p3.6 and p3.7 must be set to 1 to avoid low level asserting on scl or sda lines. when sio1 is used, external data memory access is not available.
tsc8051c1 rev. d (14 jan. 97) 22 matra mhs 8. electrical characteristics absolute maximum ratings (1) operating temperature: commercial 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . industrial 40 c to +85 c . . . . . . . . . . . . . . . . . . . . . . . storage temperature 65?c to +150?c . . . . . . . . . . . . . voltage on vcc to vss 0.5v to +7v . . . . . . . . . . . . . . voltage on any pin to vss 0.5v to vcc + 0.5v . . . . power dissipation 1w (2) . . . . . . . . . . . . . . . . . . . . . . . . notice: 1. stresses above those listed under aabsolute maximum ratingso may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. this value is based on the maximum allowable die temperate and the thermal resistance of the package. 8.1. dc characteristics t a = 0 c to +70 c; vss = 0v; vcc = 5v 10%; f = 0 to 16mhz. t a = 40 c to +85 c; vss = 0v; vcc = 5v 10%; f = 0 to 16mhz. symbol parameter min typ max unit test conditions inputs vil input low voltage, except scl, sda 0.5 0.2 vcc 0.1 v vil1 input low voltage, scl, sda (5) 0.5 0.3 vcc v vih input high voltage except xtal1, rst, scl, sda 0.2 vcc + 0.9 vcc + 0.5 v vih1 input high voltage, xtal1, rst 0.7 vcc vcc + 0.5 v vih2 input high voltage, scl, sda (5) 0.7 vcc vcc + 0.5 v iil logical 0 input current ports 1, 2 and 3 50 m a vin = 0.45v ili input leakage current 10 m a 0.45 < vin < vcc itl logical 1 to 0 transition current, ports 1, 2, 3 650 m a vin = 2.0v outputs vol output low voltage, ports 1, 2, 3, scl, sda, pwm07 (7) 0.3 0.45 1.0 v v v iol = 100 m a (4) iol = 1.6ma (4) iol = 3.5ma (4) vol1 output low voltage, port 0, ale, psen (7) 0.3 0.45 1.0 v v v iol = 200 m a (4) iol = 3.2ma (4) iol = 7.0ma (4) voh output high voltage, ports 1, 2, 3, scl, sda vcc 0.3 vcc 0.7 vcc 1.5 v v v ioh = 10 m a ioh = 30 m a ioh = 60 m a vcc = 5v 10% voh1 output high voltage, port 0, ale, psen vcc 0.3 vcc 0.7 vcc 1.5 v v v ioh =200 m a ioh = 3.2ma ioh = 7.0ma vcc = 5v 10% rrst rst pulldown resistor 50 90 (6) 200 k w
tsc8051c1 rev. d (14 jan. 97) 23 matra mhs test conditions unit max typ min parameter symbol cio capacitance of i/o buffer 10 pf fc = 1mhz, t a = 25 c icc power supply current (8) active mode 12mhz idle mode 12mhz 8.5 (6) 2.6 (6) 17 8 ma ma vcc = 5.5v (1) vcc = 5.5v (2) ipd power down current 5 (6) 30 m a vcc = 2.0v to 5.5v (3) notes for dc electrical characteristics 1. icc is measured with all output pins disconnected; xtal1 driven with tclch, tchcl = 5 ns (see figure 20. ), vil = vss + 0.5v, vih = vcc 0.5v; xtal2 n.c.; ea = rst = port 0 = vcc. icc would be slightly higher if a crystal oscillator used (see figure 17. ). 2. idle icc is measured with all output pins disconnected; xtal1 driven with tclch, tchcl = 5ns, vil = vss + 0.5v, vih = vcc0.5v; xtal2 n.c; port 0 = vcc; ea = rst = vss (see figure 19. ). 3. power down icc is measured with all output pins disconnected; ea = port 0 = vcc; xtal2 nc.; rst = vss (see figure 19. ). 4. capacitance loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the vols of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation. in the worst cases (capacitive loading 100pf), the noise pulse on the ale line may exceed 0.45v with maxi vol peak 0.6v. a schmitt trigger use is not necessary. 5. the input threshold voltage of scl and sda (sio1) meets the i 2 c specification, so an input voltage below 0.3 . vcc will be recognised as a logic 0 while an input voltage above 0.7 . vcc will be recognised as a logic 1. 6. typicals are based on a limited number of samples and are not guaranteed. the values listed are at room temperature and 5v. 7. under steady state (nontransient) conditions, iol must be externally limited as follows: maximum iol per port pin: 10 ma maximum iol per 8bit port: port 0: 26 ma ports 1, 2 and 3: 15 ma maximum total iol for all output pins: 71 ma if iol exceeds the test condition, vol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 8. for other values, please contact your sales office. rst ea xtal2 xtal1 vss vcc vcc icc (nc) clock signal p0 vcc vcc all other pins are disconnected. figure 17. icc test condition, active mode. vcc rst ea xtal2 xtal1 vss vcc icc (nc) clock signal p0 vcc all other pins are disconnected. figure 18. icc test condition, idle mode. vcc rst ea xtal2 xtal1 vss vcc icc (nc) p0 vcc all other pins are disconnected. figure 19. icc test condition, power down mode.
tsc8051c1 rev. d (14 jan. 97) 24 matra mhs vcc0.5v 0.45v 0.7vcc 0.2vcc0.1 tclch tchcl tclch = tchcl = 5ns. figure 20. clock signal waveform for icc tests in active and idle modes. 8.2. explanation of the ac symbol each timing symbol has 5 characters. the first character is always a ato (stands for time). the other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. the following is a list of all the characters and what they stand for. example: tavll = time for address valid to ale low. tllpl = time for ale low to psen low. a: address. q: output data. c: clock. r: read signal. d: input data. t: time. h: logic level high. v: valid. i: instruction (program memory contents). w: write signal. l: logic level low, or ale. x: no longer a valid logic level. p: psen. z: float. 8.3. ac parameters t a = 0 to +70 c; vss = 0v vcc = 5v 10%; 0 to 12mhz t a = 40 c to +85 c; vss = 0v; vcc = 5v 10%; f = 0 to 12mhz. (load capacitance for port 0, ale and psen = 100pf; load capacitance for all other outputs = 80 pf.) 8.4. external program memory characteristics symbol parameter 0 to 12mhz units s ym b o l p arame t er min max u n it s tlhll ale pulse width 2tclcl 40 ns tavll address valid to ale tclcl 40 ns tllax address hold after ale tclcl 30 ns tlliv ale to valid instruction in 4tclcl 100 ns tllpl ale to psen tclcl 30 ns tplph psen pulse width 3tclcl 45 ns tpliv psen to valid instruction in 3tclcl 105 ns tpxix input instruction hold after psen 0 ns
tsc8051c1 rev. d (14 jan. 97) 25 matra mhs units 0 to 12mhz parameter symbol units max min parameter symbol tpxiz input instruction float after psen tclcl 25 ns tpxav psen to address valid tclcl 8 ns taviv address to valid instruction in 5tclcl 105 ns tplaz psen low to address float 10 ns 8.5. external program memory read cycle tpliv tplaz ale psen port 0 port 2 a0a7 a0a7 instr in instr in instr in address or sfrp2 address a8a15 address a8a15 12 tclcl taviv tlhll tavll tlliv tllpl tplph tpxav tpxix tpxiz tllax 8.6. external data memory characteristics symbol parameter 0 to 12mhz units s ym b o l p arame t er min max u n it s trlrh rd pulse width 6tclcl100 ns twlwh wr pulse width 6tclcl100 ns trldv rd to valid data in 5tclcl165 ns trhdx data hold after rd 0 ns trhdz data float after rd 2tclcl60 ns tlldv ale to valid data in 8tclcl150 ns tavdv address to valid data in 9tclcl165 ns tllwl ale to wr or rd 3tclcl50 3tclcl+50 ns tavwl address to wr or rd 4tclcl130 ns tqvwx data valid to wr transition tclcl50 ns tqvwh data setup to wr high 7tclcl150 ns twhqx data hold after wr tclcl50 ns trlaz rd low to address float 0 ns twhlh rd or wr high to ale high tclcl40 tclcl+40 ns
tsc8051c1 rev. d (14 jan. 97) 26 matra mhs 8.7. external data memory write cycle tqvwh tllax ale psen wr port 0 port 2 a0a7 data out address or sfrp2 tavwl tllwl tqvwx address a8a15 or sfr p2 twhqx twhlh twlwh 8.8. external data memory read cycle ale psen rd port 0 port 2 a0a7 data in address or sfrp2 tavwl tllwl trlaz address a8a15 or sfr p2 trhdz twhlh trlrh tlldv trhdx tavdv tllax 8.9. serial port timingshift register mode symbol parameter 0 to 12mhz units s ym b o l p arame t er min max u n it s txlxl serial port clock cycle time 12tclcl ns tqvhx output data setup to clock rising edge 10tclcl133 ns txhqx output data hold after clock rising edge 2tclcl117 ns txhdx input data hold after clock rising edge 0 ns txhdv clock rising edge to input data valid 10tclcl133 ns
tsc8051c1 rev. d (14 jan. 97) 27 matra mhs 8.10. shift register timing waveforms valid valid input data valid valid 0123456 8 7 ale clock output data write to sbuf clear ri txlxl tqvxh txhqx txhdv txhdx set ti set ri instruction 01234567 valid valid valid valid 8.11. sio1 (i 2 c) interface timing symbol parameter input output t hd; sta start condition hold time 14 t clcl > 4.0 m s (1) t low scl low time 16 t clcl > 4.7 m s (1) t high scl high time 14 t clcl > 4.0 m s (1) t rc scl rise time 1 m s (2) t fc scl fall time 0.3 m s < 0.3 m s (3) t su; dat1 data setup time 250ns > 20 t clcl t rd t su; dat2 sda setup time (before repeated start condition) 250ns > 1 m s (1) t su; dat3 sda setup time (before stop condition) 250ns > 8 t clcl t hd; dat data hold time 0ns > 8 t clcl t fc t su; sta repeated start setup time 14 t clcl > 4.7 m s (1) t su; sto stop condition setup time 14 t clcl > 4.0 m s (1) t buf bus free time 14 t clcl > 4.7 m s (1) t rd sda rise time 1 m s (2) t fd sda fall time 0.3 m s < 0.3 m s (3) notes: 1. at 100 kbit/s. at other bitrates this value is inversely proportional to the bitrate of 100 kbit/s. 2. determined by the external busline capacitance and the external busline pullup resistor, this must be < 1 m s. 3. spikes on the sda and scl lines with a duration of less than 3 t clcl will be filtered out. maximum capacitance on buslines sda and scl = 400pf.
tsc8051c1 rev. d (14 jan. 97) 28 matra mhs 8.12. sio1 (i 2 c) timing waveforms t rd ;sto t su ;sta stop condition ;dat1 ;dat ;sta start or repeated start condition sda (input/output) scl (input/output) 0.7 vcc 0.3 vcc 0.7 vcc 0.3 vcc ;dat3 ;dat2 repeated start condition repeated start condition t hd t low t high t su t hd t su t su t buf t su t fd t rc t fc 8.13. external clock drive characteristics (xtal1) symbol parameter min max units tclcl oscillator period 83.3 ns tchcx high time 5 ns tclcx low time 5 ns tclch rise time 5 ns tchcl fall time 5 ns 8.14. external clock drive waveforms vcc0.5v 0.45v 0.7vcc 0.2vcc0.1 tchcl tclcx tclcl tclch tchcx 8.15. ac testing input/output waveforms input/output 0.2 vcc + 0.9 0.2 vcc 0.1 vcc 0.5 v 0.45 v ac inputs during testing are driven at vcc 0.5 for a logic a1o and 0.45v for a logic a0o. timing measurement are made at vih min for a logic a1o and vil max for a logic a0o.
tsc8051c1 rev. d (14 jan. 97) 29 matra mhs 8.16. float waveforms float float voh 0.1 v vol + 0.1 v vload vload + 0.1 v vload 0.1 v for timing purposes as port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded voh/vol level occurs. iol/ioh 20ma.
tsc8051c1 rev. d (14 jan. 97) 30 matra mhs 8.17. clock waveform data pcl out data pcl out data pcl out sampled sampled sampled state4 state5 state6 state1 state2 state3 state4 state5 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 p1 p2 float float float these signals are not activated during the execution of a movx instruction indicates address transitions external program memory fetch float data sampled 00h is emitted during this period dpl or rt out indicates dph or p2 sfr to pch transition pcl out (if program memory is external) pcl out (even if program memory is internal) pcl out (if program memory is external) old data new data p0 pins sampled p1, p2, p3 pins sampled p1, p2, p3 pins sampled p0 pins sampled rxd sampled internal clock xtal2 ale psen p0 p2 (ext) read cycle write cycle rd p0 p2 wr port operation mov port src mov dest p0 mov dest port (p1. p2. p3) (includes into. int1. to t1) serial port shift clock txd (mode 0) data out dpl or rt out indicates dph or p2 sfr to pch transition p0 p2 rxd sampled this diagram indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125ns. this propagation delay is dependent on variables such as temperature and pin loading. propagation also varies from output to output and component. typically though (t a =25 c fully loaded) rd and wr propagation delays are approximately 50ns. the other signals are typically 85ns. propagation delays are incorporated in the ac specifications.
tsc8051c1 rev. d (14 jan. 97) 31 matra mhs 9. ordering information tsc 51c1 xxx 12 16 part number 8051c1: romless version 51c1: 8kx8 mask rom temic semiconductor microcontroller product line c temperature range c : commercial 0 to 70 c i : industrial 40 to 85 c 12 : 12 mhz version 16 : 16 mhz version packaging a : pdil 40 b : plcc 44 c : pqfp 44 d : ssop 44 e : plcc 52 g : cdil 40 h : lcc 44 i : cqpj 44 b customer rom code conditioning r : tape & reel d : dry pack b : tape & reel and dry pack r a bounding option none : 12 pwm a : 4 pwm & p2x examples part number description tsc51c1xxx12ca mask rom xxx, 12 mhz, pdil 40, 0 to 70 c tsc8051c116cer romless, 16 mhz, plcc 52, 0 to 70 c, tape and reel development tools reference description anm059 application note: ahow to recognize video mode and generate free running synchronization signals using tsc8051c1/c2 microcontrollero im80c51rb40040 emulator base pctsc8051c1rb16 probe card for tsc8051c1. these products are released by metalink. please consult the local tools distributor or your sales office. product marking : temic customer p/n temic p/n ? intel 80, 82 yyww lot number

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